1. Field of the Invention
This invention relates to semiconductor devices having a V-groove isolation polycrystal backfill (VIP) structure type, and particularly to semiconductor devices of the VIP structure type having improved alignment marks and a method of manufacturing the same.
2. Description of the Prior Art
Generally, isolation between elements of a semiconductor device is indispensable to a bipolar semiconductor device, for example, a bipolar integrated circuit (IC). Such isolation can be accomplished with a PN junction isolation, an insulating material isolation or an air isolation. The insulating material isolation, particularly, a VIP structure isolation has a superior isolation ability and results in a denser integrated circuit as compared with the PN junction isolation and the air isolation. Consequently, insulating material isolation is generally used in a bipolar semiconductor device (see, for example, cf. Stephen Wm. Fields: Electronics, July 3 (1972), pp. 65-66.
In a case where a bipolar semiconductor device having a VIP structure isolation is manufactured, the VIP structure isolation and an alignment mark are (simultaneously) formed. The alignment mark is necessary for masks, i.e. pattern masks, which are used in formation of the steps of active elements, passive elements and a patterned metal layer of a semiconductor device. However, since the structure of the alignment marks which have been hitherto formed has been the same as that of the VIP structure isolation, the contour of the alignment mark has not been sharp. Such non-sharp contour is inconvenient for mask alignment operations. This inconvenience will now be explained with reference to the attached FIGS. 1 through 7.
FIGS. 1 through 6 are partial cross-sectional views of a semiconductor device having a conventional alignment mark in various stages of its manufacture by a method in accordance with prior art techniques.
A substrate 1 (FIG. 1) is made by cutting a p-type single-crystal silicon along the (100) plane and then highly polishing it. N.sup.+ -type regions 2 are produced as buried layers by a conventional technique, e.g. an ion implantation of n-type dopants. An n-type silicon semiconductor layer 3 is formed on the silicon substrate 1 by an epitaxial growth method. The surface of the silicon semiconductor layer 3 is the (100) plane. Then, a silicon dioxide (SiO.sub.2) layer 4 is formed on the silicon semiconductor layer 3 by a conventional technique, e.g. thermal oxidation of silicon. A silicon nitride (Si.sub.3 N.sub.4) layer 5 is formed on the SiO.sub.2 layer 4 by a conventional technique, e.g. chemical vapor deposition (CVD), and thus, a structure as illustrated in FIG. 1 is formed.
The Si.sub.3 N.sub.4 layer 5 is selectively etched by a conventional photolithography technique to form openings. In the openings parts corresponding to an isolation area and to an alignment mark area of the SiO.sub.2 layer 4 are exposed. Then, using the Si.sub.3 N.sub.4 layer 5 having the patterned opening as a mask, the SiO.sub.2 layer 4 is etched to form openings 6 and 7 as illustrated in FIG. 2, which is a sectional view taken along line II--II of FIG. 7. In the opening 6 a part corresponding to the isolation area of the silicon epitaxial layer 3 is exposed, and in the opening 7 a part corresponding to the alignment mark area of the silicon epitaxial layer 3 is exposed (cf. FIG. 7 being a plan view of FIG. 2). In FIG. 7 the opening 7 of the alignment mark area is in the shape of a rectangular band surrounding a portion of the Si.sub.3 N.sub.4 layer 5. However, the alignment mark area opening may have any suitable shape (e.g. a T shape, an X shape).
The portions of the silicon epitaxial layer 3 within the openings 6 and 7 are anisotropically etched with an etchant, of which the chief ingredient is potassium hydroxide (KOH), to form V-grooves 8 as illustrated in FIG. 3. A silicon dioxide layer 9 (FIG. 4) is formed by thermaly oxidizing the surface of the V-grooves 8. During the thermal oxidizing operation, the remaining insulating layer 5 acts as a mask against oxidation. A polycrystalline silicon layer 10 is formed on the entire exposed surface by a chemical vapor deposition method, as illustrated in FIG. 4. The polycrystalline silicon layer 10 is polished to leave a part of it in the V-groove only, as illustrated in FIG. 5. When the polishing operation is carried out, the edges of the remaining insulating layer 5 are broken off and the center portion of the remaining polycrystalline silicon layer 10 in the V-grooves is slightly dented, as illustrated in FIG. 5.
The remaining polycrystalline silicon layer 10 in the V-grooves 8 is thermaly oxidized to form a thick silicon dioxide (SiO.sub.2) layer 4' (FIG. 6). Thus, an alignment mark and a VIP structure of a semiconductor device are simultaneously completed, and isolated element areas 3' (FIG. 6) are formed. Then, the remaining insulating layer 5 is removed, so that a structure as illustrated in FIG. 6 is obtained.
Thereafter, a bipolar transistor or a passive element is formed in each of the isolated element areas 3' by conventional techniques which use patterned masks. Each of the patterned masks should be aligned with the above-mentioned alignment mark. However, the formed alignment mark has a non-sharp contour, since the surface of the polished polycrystalline silicon layer is concave and a large "bird's beak" is generated during the thermal oxidation of the polished polycrystalline silicon. Namely, the width W.sub.1 (FIG. 6) of a slanted side of the alignment mark is from 1.0 to 2.0 microns, usually approximately 1.5 microns.